(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to split gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memory).
(2) Description of Prior Art
A basic operation in split gate flash EEPROMs is the programming operation. In the programming operation charge is introduced into the floating gate of the crack gate flash memory cell. Traditionally when programming by source side injection, the introduction of charge into the floating gate is accomplished in two steps. In the first step, channel electrons are heated by the electric field parallel to the channel so that when they are opposite the floating gate there is a significant number of electrons with increased energy. Secondly, the electrons must overcome the gate oxide potential barrier to pass into the floating gate. The higher the electron energy and the electric field normal to the channel the easier it is to penetrate the barrier and the more efficient the charging of the floating gate. This two-step process is shown in FIG. 1. Electrons in the channel at point 1, under selected gate 2, are accelerated in passing to point 3, under the floating gate 4, by a field E1x, which is determined by the potential difference, V31, between points 3 and 1. The voltage of the selected gate, which should be low, determines the potential at point 1. The voltage applied to the top gate, 6, determines the voltage of the floating gate to which it is coupled. The voltage of the floating gate, which should be high, in turn determines the voltage at point 3. The larger is V31 the larger is the hot electron generation rate, the rate at which electrons gain energy. To enter the floating gate, such as by going from point 3 to point 5, channel electrons need to traverse the potential barrier posed by the gate oxide, 14. The rate at which electrons traverse the gate oxide barrier depends on the electron energy, the direction of the electron""s motion relative to the barrier, and the electric field, E2y, across the barrier. The electric field E2y is determined by the voltage of the floating gate, which is determined by the voltage applied to the top gate. Higher electron energy, motion more normal to the barrier and higher fields across the barrier are favorable for barrier penetration. E1x, which is perpendicular to E2y, determines electron energy and thus these two fields act independently. Furthermore the action of E1x is to accelerate electrons along the direction of the channel, which is in a direction parallel to the barrier or the least efficient direction. Only electrons that scatter and who""s scattering angle is near a right angle, so that after scattering they are moving normal to the barrier, will have a reasonable probability of traversing the barrier. To overcome these distractions in the efficiency of charging the floating gate, high voltages need be applied to the top gate. However, high voltages result in decreased reliability. It is a major objective of the invention to provide a split gate flash structure with increased floating gate charging efficiency that requires lower top gate applied voltage and thus possesses increased reliability.
Another basic operation in split gate flash EEPROMs is the erasing operation in which in which the floating gate is discharged. Traditionally the erasing operation is accomplished as shown in FIG. 2. Electrons pass from the floating gate, 4, through the gate oxide, 14, into the semiconductor region 10 under the influence of the potential difference V across the gate oxide. In the traditional structure, with planer geometry for the semiconductor region surface and for the facing floating gate surface, V is required to be large for efficient erasing. As a result high applied voltages are required which leads to decreased reliability. It is therefore a major objective of the invention to provide a split gate flash structure with increased floating gate erasing efficiency that requires lower top gate applied voltage and thus possesses increased reliability.
Hsieh et al., U.S. Pat. No. 6,228,695, shows a split gate flash memory cell having self-aligned source and with floating gate self-aligned to control gate. Hsieh et al. U.S. Pat. No. 6,229,176 shows a split gate flash memory cell with step poly with improved programming speed. U.S. Pat. No. 5,583,811 to Van Houdt et al. shows an EEPROM cell structure with enhanced injection efficiency. U.S. Pat. No. 6,091,639 to Wong shows a split gate nonvolatile memory cell that is highly scalable.
It is a primary objective of the invention to provide a split gate flash structure with increased programming and erasing speed. It is another primary objective of the invention to provide a split gate flash structure that requires lower top gate applied voltage and thus possesses increased reliability. Yet another primary objective is to provide a split gate flash structure whose cell decrease is not limited by the circuitry required to deliver the high voltage needed for traditional programming and erasing processes. It is yet another primary objective of the invention to provide a method to fabricate a split gate flash structure with increased programming and erasing speed. It is yet another primary objective of the invention to provide a method to fabricate a split gate flash structure that requires lower top gate voltage and thus possesses increased reliability. Yet another primary objective is to provide a method to fabricate a split gate flash structure whose cell decrease is not limited by the circuitry required to deliver the high voltage needed for traditional programming and erasing processes.
These objectives are achieved in the invention by a split gate flash structure in which enhanced programming speed is attained by the use of high efficiency injectors fabricated directly on the semiconductor region. With the injectors being in direct electrical contact with the semiconductor region the planarity of the semiconductor""s surface is disturbed and the injectors are so disposed that, as a consequence, erase injectors are formed, thus also enhancing the speed of the erase operation. Therefore, there is an increase in the speed of both the programming and erasing operations. Consequently, the top gate voltage can be reduced with no sacrifice in efficiency, which eliminates the need for special circuitry to achieve high voltage and thus facilitates decreasing the cell size. In addition, lower voltage results in improved reliability.
A split gate structure is disclosed for improved programming and erasing efficiency. A semiconductor region extending to the surface of a substrate has isolation regions surrounding parallel active regions. Source/drain regions in the semiconductor region are equally spaced along the active regions and are electrically connected by source/drain connecting regions, denoted source/drain towers, disposed over said source/drain regions and running perpendicular to the active regions. A multiplicity of structures denoted floating gate towers, parallel to the source/drain towers are situated between each pair of said source/drain towers. A floating gate tower having first insulating layers, disposed over the semiconductor region within the active regions crossed by the floating gate tower, separating floating gates, which exist only over active regions crossed by the floating gate tower, from the semiconductor region. A second insulating layer separates the floating gates from a top gate and a third insulating layer is disposed over the top gate. Insulator spacers are disposed over the sidewalls. The second insulating layer, top gate, third insulating layer and insulator spacers exist over the entire floating gate tower. Programming injectors are disposed against the sidewalls of the floating gate towers except where there are source/drain towers. The programming injectors are in electrical contact with the semiconductor region and taper to a sharp edge against the sidewalls of the floating gate towers at a height so that they face the floating gates. Selected gates, parallel and disposed over the active regions, are separated from the semiconductor region, the programming injectors and the source/drain towers by a fourth insulating layer.